1. SoC/ASIC/Testchip & package architecture designs for high speed Analog/Serdes, D2D, and HBM2/3/4 integrations (Server, Networking, Wireless, AI, AR). 2. Execute SI/PI/EMC design-optimization for chip/package/system integration and electrical performance optimization, e.g., eye diagram, jitter, IR/EM, system-PI, cross-talk, and SSN/SSO. 3. Develop system integration design guidelines with SI/
No requirement for relevant working experience
No management responsibility