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SHOPLINE 全球智慧開店平台，創立於 2013 年，2014 年獲選加入矽谷 500 Startups 加速器計劃，是香港多年來第二間加入的團隊，2015 年正式進入台灣市場。SHOPLINE 是致力於協助品牌一舉創建、管理線上與線下商店的一站式智

SHOPLINE 全球智慧開店平台，是提供品牌一舉創建、管理線上與線下商店的一站式智慧開店服務。 以品牌電商架站平台為核心，整合網站設計、商品管理、金物流服務以及行銷導流工具，為賣家提供簡單、好

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Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in a technical or engineering field or equivalent practical experience. 4 years of experience in procurement and supply chain management. Preferred qualifications: Experience with Interconnect supply base and technologies for server and storage infrastructure. Ability to travel and to drive change with a long term perspective across multiple functions. Ability to work in ambiguous situations, and resolve conflict

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Mechanical Engineering, Product Design, or related field, or equivalent practical experience. 5 years of experience designing mechanical components like plastic or metal parts, mechanical assemblies, printed circuit boards, or flexes. 5 years of experience using computer-aided design (CAD) tools like 3D MCAD, NX, Creo, or Solidworks. Preferred qualifications: Master's degree in Mechanical Engineering or relate

Google welcomes people with disabilities. Minimum qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience. 2 years of experience working on system-level signal integrity design, or 1 year of experience with an advanced degree. Experience with component-level and integrated system testing and high speed digital interconnect design. Experience with SI/PI design techniques, including printed circuit board routin

Minimum qualifications: Bachelor’s degree in Electrical or Computer Engineering, or equivalent practical experience. Experience with ARM-based SoCs, interconnects, and ASIC methodology. Experience with RTL design using Verilog/System Verilog and microarchitecture. Experience with a scripting language like Python or Perl. Preferred qualifications: Master’s degree in Electrical or Computer Engineering. 3 years of experience with IP design for clocking, interconnects, and peripherals. Experience wi

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 8 years of experience with verification methodology such as UVM. 6 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc. Experience with SystemVerilog, SVA, and functional coverage. Preferred qualifications: Master's degree in Electrical Engineering or a related field. Experience verifying digital systems using standard IP components/interconnects (e.g., micr

Minimum qualifications: Bachelor’s degree in Electrical or Computer Engineering or equivalent practical experience. 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology. 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture. Experience with a coding language like Python or Perl. Preferred qualifications: Master's degree or PhD in Electrical Engineerin