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Google will be prioritizing applicants who have a current right to work in Singapore, and do not require Google's sponsorship of a visa.Minimum qualifications: Bachelor's degree in Computer Science or a related technical field, or equivalent practical experience. 5 years of experience with customer-facing designing and deploying distributed data processing systems with one or more technologies. Experience with SQL databases (e.g., PostgreSQL, MySQL) and NoSQL databases (e.g., Mongo, Cassandra, DynamoDB, etc.). Experience with data modeling techniques and methodologies for traditional Online Analytical Processing or Online Transaction Processing (OLAP/OLTP) databases and modern data warehouses Preferred qualifications: 5 years of experience in managing technical client service. Experience with reading software code in one or more languages such as Java, Python, NodeJS, Golang, JavaScript. Experience in devising migration approaches, and migrating on-premise data processing systems to Cloud. Experience with designing and deploying distributed data processing systems with one or more technologies: SQL Server, MySQL, PostgreSQL, MongoDB, Cassandra, Redis, Hadoop, Spark, Flink, Kafka, Druid, Hive, HBase, Vertica, Netezza or Teradata. Knowledge of building and operationalizing data pipelines. About the jobThe Google Cloud Consulting Professional Services team guides customers through the moments that matter most in their cloud journey to help businesses thrive. We help customers transform and evolve their business through the use of Google’s global network, web-scale data centers, and software infrastructure. As part of an innovative team in this rapidly growing business, you will help shape the future of businesses of all sizes and use technology to connect with customers, employees, and partners. In this role, you will work with customers on projects to transform their business with data. You will provide consulting, solution design, and technical program management capabilities to customer engagements while guiding customer executives and technical stakeholders on project related decisions. You will serve as a liaison between the customers and product teams to drive product excellence and adoption. You will also work with Google partners currently servicing accounts to manage programs, deliver consulting services, and provide technical guidance.Google Cloud accelerates every organization’s ability to digitally transform its business and industry. We deliver enterprise-grade solutions that leverage Google’s cutting-edge technology, and tools that help developers build more sustainably. Customers in more than 200 countries and territories turn to Google Cloud as their trusted partner to enable growth and solve their most critical business problems.Responsibilities Work with customer technical leads, client executives, and partners to manage and deliver implementations of cloud solutions. Become a trusted advisor to decision makers throughout the engagement. Work with internal specialists, product and engineering teams to package best practices and lessons learned into thought leadership, methodologies, and published assets. Interact with business, partners, and customer technical stakeholders to manage project scope, priorities, deliverables, risks/issues, and timelines for client outcomes. Propose solution architectures and manage the deployment of cloud based databases, big data, and analytics solutions according to customer requirements and implement best practices. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. As an Integrated Circuit Designer, you will be part of a key team designing sophisticated advanced node CMOS products. Key Job Duties: The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets]. The management of manufacturing process of the products, including technology yield and performance of the products. The development of test programmes and procedures to ensure the products meet their performance specifications. This will include [working on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB]. The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment. Basic Qualifications Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university. 6+ years of experience supporting or developing complex analog IC designs. Required Experience: Hands-on experience in designing high-speed mixed-signal circuits, including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution and other high-speed analog circuits is a must. Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits. Solid track-record for implementation of analog circuits high-speed data transmissions. Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must. Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis. Knowledge of TIA design and drivers for optical applications is highly desirable. Experience in RFIC design for wireless or wireline communication systems is highly desirable. Strong technical independent contributor with a proven ability to drive results. Excellent teamwork, presentation, and documentation skills. Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines. Strong experience in lab chip bring-up and debugging efforts. Preferred Experience: Relevant research publications and/or patents in analog or RF IC design. Familiarity in programming/scripting languages such as Python, Matlab, or C. Experience with PCB design. Familiarity with Verilog RTL or DSP design concepts. Knowledge of optical transceivers. Expertise in ESD protection techniques and IC packaging methodologies. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.About the Role We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5nm, 3nm technology node. In this role, you will take ownership of physical implementation from RTL to GDSII, ensure timing and power closure for ultra-high-speed designs, and collaborate closely with cross-functional teams to resolve challenges unique to advanced nodes and multi-gigabit transceiver architectures. Key Responsibilities Perform full-chip and block-level physical implementation including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in TSMC 3nm. Collaborate with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power. Work on advanced physical design techniques to support multiple voltage/frequency domains, hierarchical design, and physical-aware synthesis. Handle advanced physical design topics: EM/IR analysis and power grid optimization Congestion analysis and mitigation Clock domain crossing and skew optimization RC extraction-aware placement and routing Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment. Participate in defining floorplan strategy and chip partitioning for multi-gigabit transceivers. Perform ECO implementation and support tapeout signoff activities. Ensure DRC/LVS/ANT/CELL/ERC clean database using industry-standard physical verification tools. Use industry-standard tools (e.g., ICC2, Innovus, Voltus, RedHawk, Calibre) for implementation and signoff. Develop and maintain automation scripts (Tcl, Python, Perl) for physical design flows and regressions. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field. 4+ years of experience in physical design with advanced technology nodes (preferably ≤ 5nm). Strong experience with: Floor planning, placement, CTS, routing, and IR drop mitigation Signoff checks (DRC/LVS/ANT/ERC) and debugging Timing closure collaboration with STA team Hands-on experience with tools such as Synopsys ICC2, Cadence Innovus, Calibre, Voltus. Experience in integrating high-speed IPs (e.g., SerDes, PHYs) into SoC or chiplet environments. Experience in high frequence data path, DSP designs. Solid scripting skills for automation and productivity enhancement. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job Description: As an Analog/Mixed-Signal IC Design Engineer , you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role Basic Qualifications: Pursuing a Master’s or PhD degree in EE is preferred Desired Experience: Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits Solid track-record for implementation of analog circuits high-speed data transmission. Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis. Knowledge of TIA design and drivers for optical applications is highly desirable Experience in RFIC design for wireless or wireline communication systems is highly desirable. Strong technical independent contributor with a proven ability to drive results. Excellent teamwork, presentation, and documentation skills. Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines. Strong experience in lab chip bring-up and debugging efforts. Relevant research publications and/or patents in analog or RF IC design. Familiarity in programming/scripting languages such as Python, Matlab, or C. Experience with PCB design. Familiarity with Verilog RTL or DSP design concepts. Knowledge of optical transceivers. Expertise in ESD protection techniques and IC packaging methodologies. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

For Singapore applicants:Google will be prioritizing applicants who have a current right to work in Singapore, and do not require Google's sponsorship of a visa.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Singapore; Bengaluru, Karnataka, India.Minimum qualifications: Bachelor's degree in Network Engineering or Telecom Engineering, a related technical field, or equivalent practical experience. 3 years of experience in DWDM or TCP/IP or system design operations methodology. Experience working with field operation technicians, engineers, contractors, or vendors in a telecommunications environment. Preferred qualifications: Experience with network infrastructure, rack and stack, device commissioning, and quality acceptance control. Experience planning/leading network deployments and creating deployment packages and method of operating procedures (MOPs). Experience collaborating across multiple levels and functions, and in engaging and influencing tactical and strategic decision-making. Ability to travel up to 25% of the time as needed. About the jobAs a Network Implementation Engineer, you will be the initial point of our efforts to execute deployment, maintenance, and operations of private data networks worldwide. You will work with Technical Program Managers, Network Engineers, Design and Infrastructure Engineers, Field Engineers within Google, as well as construction and telecommunications vendors and contractors, all to position your team and organization for success.You will facilitate faster, better, and more efficient, positive outcomes for the business and our customers. Your objective will be to build the world’s most reliable, cost-effective and scalable network to support all of our current and future customers and users globally. You will be an excellent communicator and collaborator, with an ability to work effectively across multiple functions inside and outside of Google to develop creative approaches to deploying and operating our Edge network globally.You will work with Network Architects and Engineers, Design Engineers, Infrastructure Engineers, Field Engineers, Strategic Negotiators and Technical Project Managers within Google, as well as construction and telecommunications Vendors and Contractors, all to position the metro’s for which you are assigned accountable for success.Google's network provides services to millions of Internet users around the world. Our metros are on the edge of our network where Google connects to its users. The Network Team is responsible for operating that network reliably and at scale. Our team owns the full life cycle of all space, power, and network assets in all of Google’s data centers and metro points of presence globally. From the foundation, we are involved from site acquisition to construction and are accountable for what space and power is delivered. We're involved in every facet of network delivery from architecture and design to installation, configuration, activation, and commissioning.Responsibilities Support and participate with design teams, deployment teams, peering negotiators, and planners as needed to deliver connectivity to the Google network. Work with Core, Transport and Edge teams to translate common network solutions into standard bill of materials (BOMs) and detailed design packages for select internal and third-parties to execute across multiple sites simultaneously, while providing technical support as necessary. Work with the NetDeploy Automation and BusOps teams to translate common network solutions into repeatable "stateless" work packages for third-party provisioners and project coordinators to execute with minimal oversight. Generate/update documentation and implementation plans (DPKs) while providing technical leadership and guidance during deployment activities, and updating and maintaining records as needed. Execute and troubleshoot capacity workflows for edge network devices in new and existing network nodes across Google's global network. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.