Responsibilities for this position involves working closely with SOC Design, SW/System, and Chipset PE/PM/PdM to validate Digital SOC chip on ATE, SLT and Bench; collaborate with Test Engineering, SLT, and Bench to develop HVM Test Solution. The role is expected from project planning to execution on Digital SOC development. Cross collaboration work is expected with SW, System, Design, Process and Customer Engineering on power and performance related tests for High Volume Manufacturing