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Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques. Preferred qualifications: Master's de
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Google welcomes people with disabilities. Minimum qualifications: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF). Preferred qualifications: PhD in Electrical Engineering or Computer Sci
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Google welcomes people with disabilities. Minimum qualifications: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in CPU or AI accelerator logic/RTL design, including microarchitecture definition and PPA optimizations. Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF). Preferred qualifications: PhD in Electrical Engineering or Computer Scienc
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Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. 18 years of experience with digital logic design principles, RTL design concepts or verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog. Experience in leading design development or functional verification team in Intellectual Property (IP) development for SoCs including Power, Performance and Area
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Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital design in ASIC. 4 years of experience in people management. Experience with RTL design using Verilog/System Verilog and microarchitecture. Experience with ARM-based SoCs, interconnects, and ASIC methodology. Preferred qualifications: Master’s degree in Electrical Engineering or Computer Engineering.
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Minimum qualifications: Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience. 3 years of experience designing Register Transfer Level (RTL) digital reasoning using SystemVerilog for Field-programmable Gate Array (FPGA)/Application-specific integrated circuits (ASICs). Experience with Application-specific integrated circuits (ASIC) design methodologies and QA flows (e.g., VCLP, Lint, CDC, RDC, SGDFT). Ex
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Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in micro-architecture and design of IPs and subsystems in Networking domain such as packet processing, bandwidth management, congestion control,
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Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel. 4 years of experience in people management, developing employees. Experience in micro-architecture and design of Machine Learning IPs or Graphics IPs, handling Low Precision/Mixed Precision Numerics. Experience in ASIC/SoC design verification, synthes
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Minimum qualifications: 5 years of experience in designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuit (ASIC). Experience in scripting language such as Perl or Python. Experience in area, power and performance optimization. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience. Experience in design and development of security blocks or crypto blocks. About the job Be part of a d
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Minimum qualifications: Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. 15 years of experience in ASIC RTL design. Experience with RTL design using Verilog/System Verilog and microarchitecture. Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: Master’s degree in Electrical Engineering or Computer Engineering. Experience driving multi-generational roadmap for IP development. Experience leading int

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