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Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem and full-chip level. Experience with debugging of full chip flows and test sequences. Experience with reusable testbench design and development at Sub System and full chip level. Experience in C/C++ or System Verilog based tests, test sequence development. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience in low-power design verification. Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Silicon Design Verification Engineer on the Google Silicon team, you will be ensuring the quality and scalability of our custom System-on-Chips (SoC) offerings. This role requires close collaboration with hardware architects and design engineers to execute comprehensive functional verification of the core SoC infrastructure and complex system-level scenarios, including the detailed verification of generic SoC features such as clocking, reset, power management, and performance. You will drive the development and maintenance of a robust, state-of-the-art testbench environment, utilizing expertise in C/C++ and SystemVerilog/Universal Verification Methodology (UVM), with a specific focus on abstracting, building, and verifying generalized system topologies to address next-generation scalability issues.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 15 years of experience with Finite Element (FE) or Design Verification, and with fabric interconnect, Network-on-Chip (NoC) design and implementation, Advanced Microcontroller Bus Architecture (AMBA) protocols, and System-on-a-Chip (SoC) integration. 6 years of experience in people management, developing employees. Experience with project management, cross-functional collaboration and stakeholders collaboration. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science. Experience in verification of memory subsystems (e.g., Double Data Rate 5 (DDR5), Low-Power Double Data Rate 5 (LPDDR5), High Bandwidth Memory (HBM)) including Physical Layer (PHY) training and Joint Electron Device Engineering Council (JEDEC) compliance. Experience in Universal Verification Methodology (UVM)-based Internet Protocols (IP) and SoC verification with excellent programming skills in Verilog, SystemVerilog, and Perl/Python. Experience in performance verification (e.g., latency, bandwidth, Quality of Service (QoS)) and collaboration with performance modeling teams. Knowledge of Design Verification (DV) fundamentals. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Lead a team of people. Set and communicate team priorities that support organizational goals. Meet with people to discuss performance and development, and provide feedback and coaching. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use. Collaborate with external and internal Computer Aided Design (CAD) teams to develop new verification solutions that can improve quality and efficiency. Manage teams, drive execution and career growth while collaborating with architecture, design, and post-silicon teams to ensure integration of verification methodology. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Senior Design Verification Engineer We are seeking talented Design Verification Engineers with proven expertise in industry-standard protocols such as PCIe and CXL. You will play a key role in the functional verification of designs, from developing block-level and system-level verification plans to writing test sequences, executing tests, and collecting and closing coverage. Responsibilities: · Develop and execute block-level and system-level verification plans. · Write and execute test sequences, and collect and close coverage. · Collaborate with RTL designers to debug failures and refine verification processes. · Utilize coding and protocol expertise to contribute to functional verification. · Develop user-controlled random constraints in transaction-based verification methodologies. · Write assertions, cover properties, and analyze coverage data. · Create VIP abstraction layers for sequences to simplify and scale verification deployments. Basic Qualifications: · Minimum of 6 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications. · Strong academic and technical background in Electrical Engineering or Computer Engineering (Bachelor’s degree required, Master’s preferred). · Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance. · Knowledge of industry-standard simulators, revision control systems, and regression systems. · Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction. Required Experience: · Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments. · Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above. · Ability to independently develop test plans and sequences in UVM to generate stimuli. · Experience writing assertions, cover properties, and analyzing coverage data. · Developing VIP abstraction layers for sequences to simplify and scale verification deployments. Preferred Experience: · Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC. · Experience with buffering and queuing with QoS on complex NOC-based SoCs. · Analyzing performance at the system level on switching fabrics. Salary: Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Senior Design Verification Engineer We are seeking talented Design Verification Engineers with proven expertise in industry-standard protocols such as PCIe and CXL. You will play a key role in the functional verification of designs, from developing block-level and system-level verification plans to writing test sequences, executing tests, and collecting and closing coverage. Responsibilities: · Develop and execute block-level and system-level verification plans. · Write and execute test sequences and collect and close coverage. · Collaborate with RTL designers to debug failures and refine verification processes. · Utilize coding and protocol expertise to contribute to functional verification. · Develop user-controlled random constraints in transaction-based verification methodologies. · Write assertions, cover properties, and analyze coverage data. · Create VIP abstraction layers for sequences to simplify and scale verification deployments. Basic Qualifications: · Minimum of 8 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications. · Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor’s degree required, master’s preferred). · Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance. · Knowledge of industry-standard simulators, revision control systems, and regression systems. · Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction. Required Experience: · Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments. · Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above. · Ability to independently develop test plans and sequences in UVM to generate stimuli. · Experience writing assertions, cover properties, and analyzing coverage data. · Developing VIP abstraction layers for sequences to simplify and scale verification deployments. Preferred Experience: · Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC. · Experience with buffering and queuing with QoS on complex NOC-based SoCs. · Analyzing performance at the system level on switching fabrics. Salary: Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Experience with accelerator architectures and data center workloads. Preferred qualifications: 2 years of experience in Silicon domain post PhD.Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal physical design convergence -timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 8 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs. Experience in verification and debug of IP/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management, congestion control desired. Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Preferred qualifications: Master's degree in Electrical Engineering or a related field. Experience with industry-standard simulators, revision control systems, and regression systems. Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units. Experience with the full verification life cycle. Excellent problem-solving and communication skills. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Measure to identify verification holes and to show progress towards tape-out. Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 4 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs. Experience in verification and debug of IP/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management, congestion control desired. Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Preferred qualifications: Master's degree in Electrical Engineering or a related field. Experience with industry-standard simulators, revision control systems, and regression systems. Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units. Experience with the full verification life cycle. Excellent problem-solving and communication skills. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Measure to identify verification holes and to show progress towards tape-out. Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Cymetrics 是亞洲領先的資安原廠之一，擁有專屬的高端資安產品。我們提供專業的紅隊演練、滲透測試和弱點掃描服務，集結了工程技術與資安專長的團隊。 團隊成員均擁有資安風險管理和滲透測試的專業知識，具有在四大管理顧問公司、領導資安服務商、知名品牌原廠的豐富經驗，且積極參與國際 CTF 競賽，並曾取得世界第三名。我們服務的客戶來自不同產業，包括政府、金融、製造業、高科技和電子商務等等。我們團隊也協助集團獲得 ISO 27001 和 ISO 27017 認證，強化集團資安治理。團隊的核心價值在於創新、專業和協作，以提供高效的資安解決方案。 身為 Cymetrics 的資安工程師，你會擔任紅隊演練、滲透測試的主要攻擊手，深入挖掘弱點，並一同與夥伴一起完成專案。在自有開發的產品中提供專業的想法與意見。一起討論並優化專案執行的成效。 Know more about Cymetrics: https://cymetrics.io/zh-tw/ TechBlog: https://tech-blog.cymetrics.io/ How to apply Please apply for this position through 👉 https://grnh.se/bfdfcf844us It will help us process your applications faster! Our Product 我們的資訊安全團隊 Cymetrics，專注於提供全面的資安評估 SaaS 平台。團隊成員均擁有資安風險管理和滲透測試的專業知識，具有在四大管理顧問公司、台灣領導資安服務商、知名品牌原廠的豐富經驗，且積極參與國際 CTF 競賽，並曾取得世界第三名，2024 年更獲得知名藍隊競賽 HITCON CYBER RANGE 第一名佳績。我們服務的客戶來自不同產業，包括政府、金融、製造業、高科技和電子商務等等。我們團隊也協助集團獲得 ISO 27001 和 ISO 27017 認證，強化集團資安治理。團隊的核心價值在於創新、專業和協作，以提供高效的資安解決方案。 Responsibilities 規劃以及執行紅隊演練、滲透測試，協助客戶發現漏洞並進行改善且驗證修復結果。與客戶進行專案會議，開會溝通，釐清並協助客戶解決問題。協助自動化資安工具開發，與軟體工程團隊一同完成自有 SaaS 產品。與產品開發團隊合作，協助改進資安產品及平台。研究網站或開源專案漏洞，將研究結果寫成文章發佈至公司的技術文章部落格。 Requirements 三年以上紅隊演練、滲透測試，善於對內部網路橫向移動與滲透。對現代 Web 框架（如React, Angular, Vue.js）和客戶端安全弱點（例如XSS, CSRF, CSP bypass, GraphQL等）理解，並熟悉其背後原理。熟悉 OWASP 測試指南和其他安全測試方法，對網頁漏洞、作業系統、網路架構有深入理解，並熟悉其背後原理。能夠清晰地整理和撰寫測試結果及修補建議，並有效地與團隊和客戶溝通。 Plus 對區塊鏈相關的資安技術有興趣 有打過知名廠商 bug bounty 或是參加過國際 CTF 的經驗 (或有同等 CVE 弱點) 擁有 OSWE、OSEP 或 OSCP 證照 (或其它同等資訊安全證照) 擅長撰寫資安相關之技術文章（漏洞研究、CTF writeup 等等） 參與過開源項目，展現對安全社群的貢獻和合作精神。 流利的中英文聽說能力，並與客戶講解滲透測試報告內容。 Cymetrics is one of the leading cybersecurity solution providers in Asia, offering exclusive high-end cybersecurity products. We specialize in professional red teaming, penetration testing and vulnerability scanning services, assembling a team with engineering expertise and cybersecurity specialization. Team members possess professional knowledge in cybersecurity risk management and penetration testing, with extensive experience in major consulting firms, leading cybersecurity service providers, and renowned brand OEMs. They actively participate in international CTF (Capture The Flag) competitions, achieving top three places globally. Our clientele spans diverse industries, including government, finance, manufacturing, high-tech, and e-commerce, among others. Additionally, our team assists the group in obtaining ISO 27001 and ISO 27017 certifications, reinforcing the group's cybersecurity governance. The core values of our team lie in innovation, professionalism, and collaboration, aiming to deliver efficient cybersecurity solutions. As a Cybersecurity Engineer at Cymetrics, you will serve as the primary attacker in red teaming and penetration testing, deeply probing vulnerabilities, and collaborating with partners to complete projects. You will contribute professional insights and opinions to our proprietary product development, engaging in discussions to optimize project execution effectiveness. Know more about Cymetrics:https://cymetrics.io/en-us/ TechBlog: https://tech-blog.cymetrics.io/ Our Product Our cybersecurity team, Cymetrics, is committed to providing a comprehensive cybersecurity assessment SaaS platform. With expertise in risk management and penetration testing, our team includes professionals from Big 4 consulting, leading cybersecurity services provider global banks, and top cybersecurity firms. Cymetrics excels in international CTF competitions, achieving a top-three global ranking and securing 1st place in the prestigious 2024 HITCON Cyber Range blue team. competition. Cymetrics supports clients across government, finance, manufacturing, high-tech, and e-commerce sectors. We’ve also secured ISO 27001 and ISO 27017 certifications for our group. Focused on innovation and collaboration, Cymetrics provides an AI security and LLM verification platform to assess AI models for vulnerabilities and Responsible AI compliance. Responsibilities Planning and executing redteam project and penetration tests, aiding clients in identifying vulnerabilities, verifying remediation, and validating fix outcomes. Conducting project meetings with clients, engaging in effective communication, clarifying issues, and assisting clients in problem resolution. Assisting in the development of automated security tools, collaborating with the software engineering team to complete proprietary SaaS products. Collaborating with the product development team to enhance cybersecurity products and platforms. Researching vulnerabilities in websites or open-source projects and documenting findings in articles published on the company's TechBlog. Requirements Three or more years of practical experience in red teaming, penetration testing and lateral movement in internal networks. Familiarity with modern web frameworks (such as React, Angular, Vue.js) and client-side security vulnerabilities (e.g., XSS, CSRF, CSP bypass, GraphQL). Familiarity with OWASP testing guides and other security testing methodologies, with a deep understanding of web vulnerabilities, operating systems, network architecture, and underlying principles. Ability to articulate and document test results, provide remediation suggestions clearly, and effectively communicate with teams and clients.Fluency in spoken and written English to explain penetration test reports to clients. Plus Interest in blockchain-related cybersecurity technology. Experience in bug bounty programs from reputable companies or participation in international CTFs (or equivalent CVE vulnerabilities).Possession of OSWE, OSEP or OSCP certifications (or other equivalent information security certifications).Proficiency in writing technical articles related to cybersecurity (vulnerability research, CTF write-ups, etc.).Involvement in open-source projects, demonstrating contributions to and collaboration within the security community.Fluency in spoken and written Chinese. How to apply Please apply for this position through 👉 https://grnh.se/bfdfcf844us It will help us process your applications faster!

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.We are seeking a Principal Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. Key Responsibilities: Design and implement high-performance digital solutions, including RTL development and synthesis. Collaborate with cross-functional teams on IP integration for processor IPS and peripherals Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm. Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows Basic Qualifications: Bachelor’s in Electronics/Electrical engineering (Master's preferred). 12+ years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation. Proven expertise in RTL development, synthesis, and timing closure. Experience with front-end design, gate-level simulations, and design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Required Expertise: Hands-on experience with processor IP (ARM/ARC) Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART Hands-on experience with complex DMA engines and FW interaction Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). Experience with block-level and full-chip design at advanced nodes (≤ 16nm). Silicon bring-up and post-silicon debug experience. Familiarity with Synopsys/Cadence tools and UVM-based design verification. Preferred Experience: Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems Understanding of PAD design, DFT, and floor planning. Experience with NIC, switch, or storage product development. Familiarity with working in design and verification workflows in a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Senior Digital Design Engineer - PCIe We are seeking a Senior Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. Key Responsibilities: Design and implement high-performance digital solutions, including RTL development and synthesis. Collaborate with cross-functional teams on IP integration for processor IPs and peripherals Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm. Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification flows Basic Qualifications / Experience Level: Bachelor’s in Electronics/Electrical engineering (Master's preferred). 8+ years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation. Proven expertise in RTL development, synthesis, and timing closure. Experience with front-end design, gate-level simulations, and design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.   Required Expertise: Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced nodes ( 16nm) Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O cycles. Hands-on experience with processor IP (ARM/ARC) Experience of working on PCIe is a must. Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART Hands-on experience with complex DMA engines and FW interaction. Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). Experience with block-level and full-chip design at advanced nodes (≤ 16nm). Silicon bring-up and post-silicon debug experience. Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.   Preferred Experience: Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus. Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems Experience of working on PCIe/UAL is a big plus. Understanding of PAD design, DFT, and floor planning. Experience in synthesis, and timing closure is a big plus. Experience with NIC, switch, or storage product development. Familiarity with working in design and verification workflows in a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.