Avatar of 李俊儀.
李俊儀
PIE, R&D Department
Profile
Posts
1Connection
Print
Avatar of the user.

李俊儀

PIE, R&D Department
With over 8 years of in-depth experience in semiconductor and optoelectronics industries, specializing in process integration, equipment optimization, and new product development. Demonstrated success in wafer-level optical components manufacturing, achieving 14% revenue growth from new products in 2024. Skilled in advanced packaging technologies including wafer-to-wafer bonding with 94-99% yield rates. Excel at leading cross-functional teams, solving complex technical challenges, and delivering results within tight schedules and limited resources.
GCSOL Tech Co., Ltd.
National Central University
臺中市, 台灣
Taiwan

Featured Resume

Uploaded on May 18th 2025

Professional Background

  • Current Status
    Employed
  • Profession
    Process Engineer
    Project Engineer
    Product Engineer
  • Fields
    Semiconductor
    AR/VR
    Electronics / Telecommunications
  • Work Experience
    6-10 years (6-10 years relevant)
  • Management
    I've had experience in managing 1-5 people
  • Skills
    Word
    Excel
    python
    PowerPoint
    Power BI
    zemax
    ANSYS Workbench
    AutoCAD
    Thinfilm deposition
    Optical Engineering
  • Languages
    Chinese
    Native or Bilingual
    English
    Fluent
  • Highest Level of Education
    Master

Job Search Preferences

  • Current Status
    Ready to interview
  • Desired Job Type
    Full-time
    Interested in working remotely
  • Desired Positions
    半導體工程師/PM/產品經理/專案管理
  • Desired Work Locations
    New Taipei, Taiwan
    Taipei City, Taiwan
    Zhunan Township, Taiwan
    Taichung City, Taiwan
    Taiwan
  • Freelance
    Part-time freelancer

Work Experience

Process Integrate Engineer, R&D Department

Nov 2019 - Present
Taichung City, Taiwan
- Led development of 250+ new products, including design, specifications, manufacturing processes and yield improvement, contributing to 14% revenue growth in 2024. - Engineered 12-inch wafer-level optical glass products for advanced packaging applications, achieving 94-99% yield rates in initial mass production after certification by tier-1 IC design companies. - Improved 12-inch wafer cleaning equipment, increasing defect removal rate from 80% to 99% while reducing process water consumption by 73%. - Modified 8-inch optical coating equipment to accommodate 12-inch products while maintaining film thickness uniformity of 2nm, requiring only 45% of the investment compared to new equipment. - Established Advanced Product Quality Planning (APQP) processes, including FMEA/CP/MSA/SPC/PPAP, leading to successful IATF 16949 certification in 2024. - Led yield improvement projects, evaluating and implementing 12-inch AOI defect detection systems, reducing defect density from 0.7 to 0.02 ea/mm² and improving product yield to 98%. - Designed and manufactured light-shielding optical components incorporated into consumer electronics mobile products launched in 2021. - Built and managed engineering team, interviewing and training 70% of new engineers while overseeing project schedules and work allocation. - Assessed equipment and established 12-inch glass wafer production line, utilizing DOE, FEA (thermal/stress), failure/yield analysis and user interviews to improve equipment and manufacturing processes, designing 300+ components and reducing substrate thickness by 85% to 100μm.

Thin Film Process Engineer, R&D Department

Optorun Co. Ltd
Full-time
Aug 2017 - Nov 2019
2 yrs 4 mos
Taichung City, Taiwan
- Successfully transitioned first-generation TOF Sensor coating equipment from R&D to mass production in semiconductor and optical factories. - Collaborated closely with seven clients across Taiwan and Korea to implement customized design changes for new coating equipment. - Identified and resolved root causes through process monitoring, yield analysis, optical simulation and materials analysis, resulting in improved facility system stability, material purity and specific mechanical components. - Developed new coating materials, process methods and optical component structures, securing two patents.

Lithography Process Engineer

Dec 2016 - Jul 2017
8 mos
Tainan City, Taiwan
- Managed I-line and DUV lithography processes, including verification of alternative photoresist sources and equipment - Analyzed production data to improve yield and production capacity - Maintained Statistical Process Control (SPC) and Advanced Process Control (APC) systems.

Education

Master’s Degree
材料科學工程學系
2014 - 2016
Description
Publish : Low temperature plasma-assisted growth of Indium oxide nanostructures and applied as antireflection structure for solar cells
Bachelor’s Degree
材料科學工程學系
2010 - 2014
Description
Skills: Microsoft PowerPoint · 簡報 · Microsoft Excel