• 5 Years of experience in DPS processes, 2 years in WLCSP bumping, and 1 year in CIS processes • Responsible for process optimization, failure mode analysis, SPC monitoring, Yield monitoring, NPI launch, cost reduction, UPH improvement, DOE, CIP, and new equipment qualification Accomplishments • Resolved glass crack defects in the glass bonding process, reducing wafer scrap ratio to 0%. • Qualified and implemented a second-source protective liquid for laser grooving, saving 29.5% in costs. • Collaborated with IT and Production Management teams to develop a Tableau dashboard integrating lot history and material batch data for real-time visualization. • Built a Tableau report to visualize and summarize rework status across all processes. • Won 2nd place in the company's CIP competition by reducing hold ratio of tape residue defects from 4.9% to 0% and yield loss from 1481 ppm to 459 ppm. • Reduced backside chipping defect yield loss by optimizing dicing dressing recipe, cutting hold ratio from 5.47% to 0% and yield loss from 1333 ppm to 646 ppm. • Partnered with IT and AI teams to develop a real-time process monitoring system through AYEDAS (Advanced Yield Enhancement Data Analysis System). • Developed dicing processes for multi-chip and non-ground wafers. Approved and implemented second-source parts vendor for sputtering, achieving 34% cost savings. • Implement a second pre-clean chamber of the Applied Endura sputtering tool to handle incoming wafers with arcing issues.

Accomplishments • Participated in Apple Mac Pro manufacturing established an anodizing production line and supported mass production ramp-up. • Assisted in the implementation of dual-acid chemical polishing, achieving a 50% reduction in process time.