My career began at Micron Technology, where I served as a Front-End and Mid loop Process Integration Engineer. In this role, I was responsible for optimizing process capabilities, as well as establishing and modifying process management projects. My focus was on increasing wafer yield and lowering production costs, collaborating across various departments. My expertise covers the entire manufacturing process, especially in DRAM operations, where I've worked on the STI isolation and RDL transfer processes. I accumulated two years of experience in this position. Micron ADTT PI Engineer (2021-2023) • FEOL LOOP PI - 1β DDR5 3 products passed NPI with up to yield 72.9% (2023) - Improve yield and quality to meet the T3~T1 qual (2023) • MOL2 LOOP PI - Optimize process parameters to achieve 0.1% improvement on yield (2021-2023) - Ensure process capability under offload and de-stacking and evaluate 0.15% yield loss risk management with 37.5K WPD production benefits (2022-2023) - 1α DDR4 6 products show yield 90.6%, reaching MY 90.4% and continuing to improve (2022) - Q Time for establishing and modifying process intervals is reduced by 1hr to reduce cycle time (2022)