I am Akula Harsha Vardhan Sai Mohan, a Physical Design Engineer with one year of experience in ASIC backend design, covering Floorplanning, Placement, CTS, Routing, and Timing Closure (STA). I have hands-on experience in 28nm technology and good knowledge of Synthesis and scripting using TCL and Perl. Passionate about VLSI design, I focus on improving design quality, timing performance, and power optimization. I am currently seeking challenging opportunities as a Physical Design Engineer in the semiconductor industry.