Hardware Design Engineer Sep.2022-Dec.2024  Participated Project: AI Server Sep.2022-Dec.2023 Platform: AMD SP5 • Served as the owner of the system’s management board. • Resolved a critical BMC sequence issue during EVT and obtained customer approval to proceed to DVT • Maintained zero BOM errors from EVT through PVT stages • Independently completed I2C, SPI, GPIO, and HW logic validation reports during EVT to PVT • Collaborated closely with cross-functional teams to track and resolve issues based on priority level > P0 (high): updated 3 times per week > P1 (medium): updated 2 times per week > P2 (low): updated biweekly • Provided on-site support for management board function test and L10 system testing and delivered troubleshooting guides that improved production efficiency by 66.7% • Achieved replacement coverage to 97% for 2nd/3rd sources of management board  Participated Project: Compute Server Jan.2024-Dec.2024 Platform: AMD SP5 • Developed a custom test script to accelerate reproduction of a low-frequency issue with a 0.3% failure rate, improving debugging efficiency • Verified the solution using the script by running five times the normal test cycles to ensure issue closure • Set up a debug station during on-site support for L10 and L11 testing, increasing production efficiency by 50% • Traveled to the Mexico factory during the PVT stage to support production, collaborating with local production and test engineers to successfully deliver the first batch of 35 server racks within the first month • Documented the issue resolution SOP notes to share with incoming support engineers to help them quickly resolve known issues Senior Hardware Design Engineer  Participated Project: Storage Server Jan.2025-Jun.2025 Platform: Intel EMR • Involved in a mother board schematic design • Contributed to the board-level design and achieved tape-out under a tight five-week schedule • Develop GPIO table(FPGA, BIC, PCH) by collaboration with cross-function teams • Completed tape-out check list including: > Review high speed routing of PCB layout to reach Intel spec requirement, made the EQL for PCIe, SPI and DMI interfaces >Main chips checklist (CPU, BIC) >All interface schematic check list >PCB layout check list • Resolved BIC sequence and UART interface issues during the bring-up phase, successfully bringing up the system • Co-work with EA team to complete HW validation of mother board in six weeks

Arima Communications Hardware Design Engineer Oct.2017-Oct.2018  Participated Project: Automotive Smart Rearview Mirrors • Maintained BOM of the system and achieved zero-BOM-error target during EVT to PVT stages • Improved replacement coverage from 90% to 95% for 2nd/3rd sources