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施詠皓
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施詠皓

學生
目前就Georgia Tech 碩一,掌握IC desgin 的設計流程並熟習運用EDA相關工具,主要研究方向為類比及混合訊號的晶片設計,熟悉市面上現有的晶片產品及半導體製造,希望在2024暑假有機會進入業界實習
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Purdue University
Georgia Institute of Technology
台灣台中
타이완

Featured Resume

Uploaded on 4월 24일 2024

Professional Background

  • Current status
    Studying
  • Profession
    Electronics Engineer
  • Fields
  • Work experience
    Less than 1 year (Less than 1 year relevant)
  • Management
  • Skills
    IC Design
    VLSI
    Hspice、Finesim、Custom Explorer、Virtuoso、 Laker、DRC、LVS、LPE、StarRC
    COMOSOL
    Verilog
  • Languages
    English
    Fluent
    Chinese
    Native or Bilingual
  • Highest level of education

Job search preferences

  • Desired job type
    Intern
    Interested in working remotely
  • Desired positions
    暑期實習生
  • Desired work locations
  • Freelance

Work Experience

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教學助教

Purdue University
Part-time
9월 2022 - 12월 2022
4 mos
United States
• 開設課後輔導時間確保學生了解半導體元件的重要內容 • 協助教授設計考試及作業的問題並進行批改
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研究助理

5월 2022 - 8월 2022
4 mos
完成 “A High Resolution Time to Digital Convertor on Chip Using Vernier Delay Line Architecture” 論文的撰寫 • 使用 Hspice 和 Cadence Virtuoso 完成 IC 線路的布局並使用 FPGA 來進行晶片的驗證 • 使用 Vernier Delay Line 的架構已達到 45 皮秒的解析度 • 使用台積電 .18製程進行製造

Education

Master of Science (MS)
Electrical engineering
2023 - 2025