- Led development of advanced node (N7/N5/N3) SoC products including SSD, CPU, GPU, and test chips. - Improved product quality through DPPM reduction and S2S gap analysis via CAVS/DVS DOE and custom test structures. - Acted as cross-functional bridge between design and foundry teams for DFT, debug, and volume manufacturing. - Drove yield, reliability, and performance enhancements through silicon data analysis and collaborative problem- solving.

- Collaborated with RTL, DFT, and layout teams to ensure manufacturability and pre-silicon yield robustness. - Performed process corner analysis and early yield ramp planning on advanced nodes.

- Assisted in failure analysis and DOE execution to identify root causes of early-life failures and optimize production testing windows. - Collaborated with foundry and testing teams to address product anomalies and improve qualification robustness. - Worked on analog and PMIC product lines, supporting product characterization, reliability, and yield ramp during NPI

- Led FinFET CMOS technology ramp for 20nm, 16nm, 10nm, and 7nm (EUV) platforms. - Cut defect rates to <1% and improved line yield >30% via integrated process solutions. - Boosted Ring Oscillator performance >20% through electrical parametric analysis and process tuning. - Supported monthly wafer output scale-up from 100K to 150K wafers within 6 months.