Responsibilities
○Led hardware design from schematic to EVT/DVT, reducing design iterations by approximately 30% through early integration of firmware requirements, proactive resolution of mechanical constraints with ME, and prompt mitigation of validation issues.
○Transformed IC reference designs into production-ready PCB platforms, optimizing signal integrity, power efficiency, and cost through close collaboration with layout and supplier engineers.
○Drove root-cause analysis and implemented design fixes for electrical and mechanical issues pre-NPI, increasing validation efficiency by 10% and ensuring a seamless transition to mass production.
Projects
Consumer Brand (Tier1 customer)
USB 3.2 Gen2 (10Gbps) / Gen2x2 (20Gbps) – Supporting TLC NAND up to 4TB (X9Pro/X10Pro)
USB 3.2 Gen2 (10Gbps) / Gen2x2 (20Gbps) – Supporting QLC NAND up to 8TB (X6/X8/X9/X10)
○Cost Optimization
– Achieved 99.7% production yield through BoM optimization, DFM-oriented layout refinement, and minimized design iterations.
○High-Speed PCB Layout Optimization
– Developed ergonomic, mass-producible PCB stack-up with optimized component placement and balanced high-speed routing for signal integrity.
○Board-Level Implementation
– Converted IC reference designs into manufacturable PCB platforms, improving signal integrity and power efficiency.
○Reliability Assurance
– Ensured design robustness through cross-functional validation; product achieved 4,000+ Amazon reviews with an average 4.5★ rating.
USB 4 Gen3x2 (40Gbps) – Supporting TLC NAND up to 4TB (no bus switch) or 32TB (with bus switch, estimated)
○Cost Optimization
– Optimized BoM during prototype development to reduce material cost and streamline validation.
○Design Enhancement
– Developed high-speed PCB layouts with mass-producible stack-up, optimized component placement, and routing for superior signal integrity.
PCIe Gen5, M.2 2280 – Supporting TLC NAND up to 4TB
○Cost Optimization
– Optimized BoM during prototype development to reduce design iteration costs.
○Design Enhancement
– Developed PCB layouts with mass-producible stack-up, optimized component placement, and balanced high-speed routing for signal integrity.