就活ツール
料金プラン
Avatar of William Chen.
William Chen
Hardware Deputy Manager
プロフィール
投稿
0つながり
印刷
Avatar of the user.

William Chen

Hardware Deputy Manager
Hardware Design Engineer | Collaborative PCIe, SATA, and USB4 Specialist | Expert in PCB Optimization & System Integration | Open to Global Server, AI, and Wearable Hardware Roles (Taiwan)
Quanta Storage Inc.
Tamkang University
台北市, 台灣
台湾

職歴・バックグラウンド

  • 現在の状況
    求職中
  • 専門分野
    Hardware Engineer
    Electronics Engineer
  • 業界分野
    電子・電気通信
    家電製品
    Hardware
  • 職務年数
    10〜15年 (10〜15年 関連経験)
  • 管理経験
    私は1~5人人の管理経験があります
  • スキル
    Allegro
    PADS
    CAM350
    OrCAD
  • 最終学歴
    大学

求職希望

  • 現在の状況
    積極的に転職活動中
  • 希望の雇用形態
    フルタイム
    リモートワークに興味あり
  • 希望職種
    AI engineer,Hardware design engineer,IC application engineer
  • 希望勤務地
    New Taipei, Taiwan
    Taipei City, Taiwan
  • フリーランス

職務経験

Deputy Manager

Quanta Storage Inc.
フルタイム
4月 2020 - 10月 2025
5 年 7 ヶ月
Responsibilities ○Led hardware design from schematic to EVT/DVT, reducing design iterations by approximately 30% through early integration of firmware requirements, proactive resolution of mechanical constraints with ME, and prompt mitigation of validation issues. ○Transformed IC reference designs into production-ready PCB platforms, optimizing signal integrity, power efficiency, and cost through close collaboration with layout and supplier engineers. ○Drove root-cause analysis and implemented design fixes for electrical and mechanical issues pre-NPI, increasing validation efficiency by 10% and ensuring a seamless transition to mass production. Projects Consumer Brand (Tier1 customer) USB 3.2 Gen2 (10Gbps) / Gen2x2 (20Gbps) – Supporting TLC NAND up to 4TB (X9Pro/X10Pro) USB 3.2 Gen2 (10Gbps) / Gen2x2 (20Gbps) – Supporting QLC NAND up to 8TB (X6/X8/X9/X10) ○Cost Optimization – Achieved 99.7% production yield through BoM optimization, DFM-oriented layout refinement, and minimized design iterations. ○High-Speed PCB Layout Optimization – Developed ergonomic, mass-producible PCB stack-up with optimized component placement and balanced high-speed routing for signal integrity. ○Board-Level Implementation – Converted IC reference designs into manufacturable PCB platforms, improving signal integrity and power efficiency. ○Reliability Assurance – Ensured design robustness through cross-functional validation; product achieved 4,000+ Amazon reviews with an average 4.5★ rating. USB 4 Gen3x2 (40Gbps) – Supporting TLC NAND up to 4TB (no bus switch) or 32TB (with bus switch, estimated) ○Cost Optimization – Optimized BoM during prototype development to reduce material cost and streamline validation. ○Design Enhancement – Developed high-speed PCB layouts with mass-producible stack-up, optimized component placement, and routing for superior signal integrity. PCIe Gen5, M.2 2280 – Supporting TLC NAND up to 4TB ○Cost Optimization – Optimized BoM during prototype development to reduce design iteration costs. ○Design Enhancement – Developed PCB layouts with mass-producible stack-up, optimized component placement, and balanced high-speed routing for signal integrity.
Logo of the organization.

System Engineer

10月 2018 - 3月 2020
1 年 6 ヶ月
Responsibilities ○Led memory module design and validation across SATA/USB/SD interfaces, driving cross-functional initiatives with firmware, reliability, and mechanical teams to achieve optimal speed, power efficiency, and thermal compliance. ○Transformed controller and NAND reference designs into manufacturable modules, optimizing PCB layout, SI/PI performance, and early risk mitigation to support reliable mass production. ○Drove cross-functional qualification and root-cause analysis, resolving design constraints and thermal/stress issues ahead of NPI, boosting development efficiency and production readiness. Projects Designed custom SATA 3.0 (2.5") and M.2 2280 SSD solutions based on SMI controllers Developed custom CFA 6.1, USB 3.0, and SD 3.01 storage solutions using third-party controllers
Logo of the organization.

Senior Application Engineer

Alcor Micro Corp
フルタイム
10月 2011 - 8月 2018
6 年 11 ヶ月
Taipei City, Taiwan
Responsibilities ○Led the development of custom RDK and test platforms for SSD/USB/SD controller validation, enabling rapid prototype deployment and successful IC verification, while providing critical documentation for controller datasheets and application notes. ○Transformed Xilinx FPGA evaluation boards into robust hardware validation platforms, enabling precise SI/PI and functional testing, and authored PCBA application notes to guide cross-team usage. ○Drove cross-functional problem-solving between firmware and silicon teams, leading to timely resolution of bring-up and design issues and consolidation of test results into controller datasheets to ensure consistent technical alignment and product readiness. Projects AU87100(USB 3.0 Flash Controller) AU7510/AU7511(SATA 3.0 Flash Controller)

Associate Hardware Engineer

Dynacolor Inc.
フルタイム
8月 2010 - 9月 2011
1 年 2 ヶ月
Taipei City, Taiwan
Responsibilities ○Led BoM management and updates for IP cameras and high-speed domes, ensuring accurate ERP tracking and smooth NPI preparation. ○Transformed design lists and engineering changes into manufacturable BoMs, supporting efficient validation builds and system testing. ○Drove PCBA assembly and cross-functional reviews, identifying and resolving hardware issues early to ensure timely prototype readiness and accelerate product release. Projects DH720(Indoor)/DH820(Outdoor)

学歴

工学士(BEng)
Electrical Engineering
2005 - 2009
3.45/4 GPA