◆ Integrated Circuit Verification -- Verify Serdes interface DisplayPort 1.4/2.0 data link layer (MAC Layer) in monitor IC. -- Verify MIPI C-PHY/D-PHY/A-PHY in automotive IC. -- Verify mixed-signal of Analog Combo PHY model composed of DisplayPort and USB. ◆ Tool and Skills -- Testbench Building: Creating testbench in Verilog and SystemVerilog for each DUT to validate checkpoints. Also using Python to build reference model as golden to be compared. -- Script Automation: Using Perl script to auto-include related files and execute the compilation. -- Issue Identifying: Tracing root cause from unexpected error report via waveform(Verdi). -- Cron Regression: Automatically re-run all testcases when RTL updated. -- Architecture Visualization: Drawing block diagram with Visio to clearly explain test plans. -- Cross-departmental Discussion: Resolving RTL bugs and firmware pattern flow issues through effective communication.

Electricity (III) Engineering Mathematics: Complex Variable