Advanced Package Technology (APT) 2.5D, 3D CoWoS, CPO (SoIC-X-CPh) NPI engagement - Team leader with early engagement in CPO (EIC, PIC integration) solution (COUPE 2.0) - Product owner of CoWoS from floorplan design engagement to NPI development

Advanced logic technology early engagement for N2 nanosheet and FinFET (N3 ~ N16) NPI bring up - Team leader with early N2 nanosheet pathfinding in performance, mask, offering and weakness - Product owner of N3, N5, N7, N12, N16 and even mature technology Broad ASIC product NPI development experience including HPC (Al, Datacenter, CXL-Switch), automotive-like (EV, Solar panel), consumer, memory pooling application End to end full turnkey delivery from (New Product Introduction) NPI to HVM production experiences - Foundry interface from design rule, DRC sign-off, spice, corner skew readiness, traceability to yield DPPM ramps, performance / functional CIP optimization and stability control - NPI project owner from prototype shipment, ATE CP, FT bring up, skew characterization to final device & package qualification - Electrical and physical failure analytics (EFA, PFA) as production, RMA driven test coverage, quality and supply chain enhancement

MEMS IC products coordinator of pressure and automotive motion sensor - RMA and R&D early qualification through EFA, PFA and functional test.

Advanced foundry FinFET logic process development experience through N3/N4/N5/N6/N7 nodes - Team leader and CIP project owner of Multi-patterned-gate loop (Vt-tunning) and FEOL S/D loop Coordinator of KPI, system and defense

Performance ramps with core device RO% & flicker noise +2~5% as N/P RChanel, EOT, CET reduction - Source / drain junction profile optimization through [P] dopant with double annealing - Overall STR / process / tooling / SPC / SOP / defense system control and development - Individual development: Best newcomer, and competition award