• Journal Paper

1. Optimizing Computer Vision Algorithms with TVM on VLIW Architecture Based on RVV, Meng-shiun Yu, Hao-Chun Chang, Chong-Teng Wang, Yu-Wei Tien, Tai-Liang Chen, Jenq-Kuen Lee, Journal of Supercomputing, Volume 81, article number 172, 2025.
2. Case Study: Optimization Methods with TVM Hybrid-OP on RISC-V Packed SIMD, Meng-shiun Yu, Chuan-yue Yuan, Tai-liang Chen, and Jenq-kuen Lee, IEEE Access, vol. 12, pp. 64193-64211, 2024.
3. Support NNEF Execution Model for NNAPI, Yuan-Ming Chang, Chia-Yu Sung, Yu-Chien Sheu, Meng-Shiun Yu, Min-Yih Hsu, and Jenq-Kuen Lee, Journal of Supercomputing, 77, 10065-10096, Springer, 2021.
4. NNBlocks: A Blockly Framework for AI Computing, Tai-Liang Chen, Yi-Ru Chen, Meng-Shiun Yu, and Jenq-Kuen Lee, Journal of Supercomputing, 77, 8622-8652, Springer, 2021

• Conference Paper

1. Enhancing RISC-V ISA to Support Sub-FP8 Quantization for Machine Learning Models, Meng-shiun Yu, Jhih-Kuan Lin, Fu-Jian Shen, Jenq-Kuen Lee, RISC-V Summit, Santa Clara, USA, Nov. 2024. (Poster)
2. Developing an LLVM Backend for VLIW RISC-V Vector Extension Architectures, Hao-Chun Chang, Jhih-Kuan Lin, Meng-Shiun Yu, Tai-Liang Chen, and Jenq-Kuen Lee, Euro LLVM, Vienna, Austria, April 2024 (Poster)
3. Verification of the RISC-V Vector Extension for the Gem5 Simulator, Chong-Teng Wang, Meng-Shiun Yu and Jenq-Kuen Lee, CTHPC, May. 2024.
4. An AI Accelerator Simulator for 2D Mesh Architecture, Yu-Wen Shao, Chao-Lin Lee, Meng-Shiun Yu and Jenq-Kuen Lee, CTHPC, May. 2023.
5. The Support of MLIR HLS Adaptor for LLVM IR, Geng-Ming Liang, Chuan-Yue Yuan, Meng-Shiun Yu, Tai-Liang Chen, Kuan-Hsun Chen, and Jenq-Kuen Lee, ICPP EMS 2022, Bordeaux, France, Aug. 29 - Sep. 1, 2022. (Virtual).
6. C++OpenCL4TVM: Support C++OpenCL Kernel for TVM NN Operators, Po-Yao Chang, Tai-Liang Chen, Yu-Tse Huang, Meng-Shiun Yu, Jenq-Kuen Lee, IWOCL 2022 (poster paper), 2022. (also in ACM proceeding article No.: 27, Pages 1 - 2)
7. Optimization with TVM Hybrid OP on RISC-V with P Extension, Chuan-Yue Yuan, Meng-Shiun Yu, Chao-Lin Lee, Chun-Chieh Yang, and Jenq-Kuen Lee, TVMcon 2021, Seattle, Dec. 15-17, 2021
8. Accelerating NNEF framework on OpenCL devices using clDNN, Meng-Shiun Yu, Tai-Liang Chen and Jenq-Kuen Lee, IWOCL 2020, Germany, May 2020 (poster paper). (also in ACM proceeding article No.: 20, Pages 1 - 2)
9. A Robot Vision System for Visual Surveillance, M. S. Yu, H. Wu, H. Y. Lin, International Journal of Innovative Computing, Information and Control, Vol. 10, No. 4, pp. 1267-1274, Aug. 2014.
10. Lane departure and front collision warning using a single camera, H. Y. Lin, L. Q. Chen, M. S. Yu, International Symposium on Intelligent Signal Processing and Communication System, pp. 64-69, Nov. 2012. 
11. A visual surveillance system for mobile robot using omnidirectional and PTZ cameras, MS Yu, H Wu, HY Lin, Proceedings of SICE Annual Conference, pp. 37-42. Aug. 2010.

• Google Research Project with NTHU

• DSP Applications and Performance Explorations with RISC-V Extensions. (2023 ~ 2024)

• Compiler Directives and Optimization Methods for Sharding AI Models. (2024 ~ 2025)

• Using LLM models to optimize LLVM compiler IRs and AI compiler optimizations. (2024 ~ 2025)

• Open-Source Contributions(TVM and MLC LLM)

• Optimized computer vision algorithm and deep learning models on RISC-V hardware under the TVM framework, including meta-scheduling and adding support for custom instructions based on RISC-V.

• Developed a new code generator and runtime for TVM on Android, enabling neural network inference on custom hardware accelerators using Android Neural Networks API (NNAPI). (Co-authored-by Ming-Long Huang and Ming-Zhang Huang)

RFC: https://discuss.tvm.apache.org/t/rfc-109-add-a-new-backend-nnapi-for-byoc/17717

• Added MLC LLM support and optimization for vision language model(Phi 3 vision).

PRs:  https://github.com/search?q=repo%3Amlc-ai%2Fmlc-llm+mengshyu&type=pullrequests

• Academic Projects(National Science and Technology Commission of Taiwan)

• Design sub-FP8 instruction based on RISC-V ISA.

Model quantization has become an essential optimization strategy for improving performance in machine learning. It reduces data types from 32-bit and 16-bit to lower-bit formats, such as 8-bit, 6-bit, and 4-bit, in both integer and floating- point data types. However, the current RISC-V instruction set lacks support for floating-point formats below 8 bits, includ- ing FP8, 6-bit, 4-bit, and other sub-byte precision formats. This research proposes extending the RISC-V ISA to support sub-FP8 operations. We design custom instructions that enable RISC-V CPUs to execute sub-FP8 computations directly, enhancing machine learning workloads’ performance and energy efficiency. By integrating with AI compiler frameworks such as TVM and MLC LLM.

• Hardware-aware Graph Partition for Mobile Inference Acceleration

Modern smartphones integrate various specialized hardware units, such as CPUs, GPUs, DSPs, and accelerators, each tailored to specific computational tasks. Many mobile systems provide native neural network APIs to leverage these hardware units efficiently. However, combining compiler-aided optimizations with NN API backends can further enhance performance. This paper introduces a generic approach for hardware-aware graph partitioning to accelerate mobile inference. We profile the operators used in the model on supported hardware and then use the profiling data to create a cost model. Based on this cost model, we apply a graph partitioning strategy to maximize computation graph performance on mobile devices.

• Apply LLM on compiler optimization for embedded devices.

Large Language Models (LLMs) have been successfully applied in various fields, such as natural language processing, programming language development, and unstructured data organization and analysis. However, their application in the field of compiler optimization is still limited. This research aims to leverage LLMs to enhance and automate compiler optimization for embedded devices, focusing on key performance metrics such as code size, execution time, hardware utilization, and memory usage. Our goal is to use LLMs to identify the optimal combinations of LLVM compiler optimizations for embedded devices. LLVM optimizations can be categorized into target-independent IR optimizations and target-dependent instruction-level optimizations. LLVM opt provides a series of optimization functions that can be executed repeatedly or combined with other optimizations. This research will address the challenge of finding the best optimization strategies for different performance metrics among the numerous possible combinations. By leveraging open LLM models, we aim to identify the most effective optimization strategies tailored to different hardware and optimization combinations, ultimately enhancing the performance of embedded devices.