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What Cake R U? ProNewUnlock your workplace personality in 3 minutes and discover your unique strengths!ResumeCreate your job-winning resume using our free resume builder.Resume BuilderMake a resume for free.Resume TemplatesAccess our extensive library of professional & ready-to-use templates.Resume ExamplesGet inspired by real resume examples to create your own.Occupation GuideAccess resume writing guides tailored for different professions.Resume HelpGet expert advice on all things resume from our team of recruitment specialists.Cake AI Resume CheckerAnalyzes your resume using Cake AI for detailed feedback.- Success StoriesBusiness ExcellenceAbout CakeFeatured Reads
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Create your job-winning resume using our free resume builder.
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Showcase your skills and projects with a professional portfolio.
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Utilize our Cake AI-powered products to accelerate job search and talent match.
What Cake R U? ProNew
Unlock your workplace personality in 3 minutes and discover your unique strengths!
Resume
Create your job-winning resume using our free resume builder.
Resume Builder
Make a resume for free.
Resume Templates
Access our extensive library of professional & ready-to-use templates.
Resume Examples
Get inspired by real resume examples to create your own.
Occupation Guide
Access resume writing guides tailored for different professions.
Resume Help
Get expert advice on all things resume from our team of recruitment specialists.
Cake AI Resume Checker
Analyzes your resume using Cake AI for detailed feedback.
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馬達設計工程師 @鑫元鴻實業股份有限公司2022 ~ Present
・
工程師
Within one month
劉祥樺 (Hsiang-Hua Liu) Taichung City, Taiwan 出生於1993年3月，畢業於逢甲大學資訊電機工程碩士學程，具備五年電動機設計與優化經驗，熟悉Ansys Maxwell與Motor CAD等模擬工具，能結合理論與實務優化馬達性能， 曾完成感應馬達及直流無刷馬達產品優化 。 碩士期間學習Python與AI
Employed
・
Ready to interview
Taiwan
Full-time / Interested in working remotely
4-6 years
逢甲大學(Feng Chia University)
・
資訊電機工程碩士學位學程
Staff Package Thermal Engineer @Alchip Technologies2023 ~ Present
・
熱傳工程師(Thermal Engineer)
Within one month
Ken Chen Thermal Engineer I’m a thermal engineer with 12+ years of hands-on experience in heat transfer, CFD simulation, and IC package/system-level thermal design. My background spans across leading companies such as Alchip, Wistron, Foxconn, and Delta, where I’ve worked on thermal solutions for APs, switches, servers, and advanced IC packaging (2.5D/3DIC, CoWoS). I specialize in: -System & package-level thermal architecture -CFD modeling (Flotherm, ANSYS, 6SigmaET, Celsius) -Cross-functional collaboration (ME, EE, PM, ID, Layout) -Thermal validation and optimization from EVT to MP I enjoy solving complex
Employed
・
Ready to interview
Taiwan
Full-time / Interested in working remotely
10-15 years
National Taipei University of Technology
・
機械工程學系
Senior-engineer @台灣立訊精密有限公司 Luxshare-ICT Co., Ltd.2022 ~ Present
・
資深工程師，技術主管
Within one month
ChunKai Chen 陳俊愷 1993/5/8 Senior Product Design Engineer Mechanical Design/ TA/ FEA/ FACA/ Cross-Functional Collaborating E-mail: [email protected] Mobile:Taoyuan City, Taiwan About Mechanical Engineer with 6+ years of experience specializing in precision design and development of Voice Coil Motors (VCMs) for camera modules. Skilled in FEA (Static, EM, Dynamic), DFM, and cross-functional team leadership. Detail-oriented, structured, and passionate about technical challenges and continuous product improvement. Skills PTC Creo SOLIDWORKS NX MINITAB FEA ANSYS Workbench ANSYS MAXWELL
Employed
・
Open to opportunities
Taiwan
Full-time / Interested in working remotely
4-6 years
國立虎尾科技大學 National Formosa University
・
Mechanical and Electro-Mechanical Engineering
Employed
・
Open to opportunities
Taiwan
Full-time / Interested in working remotely
6-10 years
南台科技大學
・
機械系自動化控制組Past
Business Development @瑞福生醫 CYTOPACX BioMedicine Co., Ltd.2022 ~ 2024
・
業務人員
Within one month
Unemployed
・
Open to opportunities
Taiwan
Full-time / Interested in working remotely
4-6 years
國立臺灣海洋大學 National Taiwan Ocean University
・
System Engineering and Naval ArchitectureMechanical Design Engineer @INNOLUX CORPORATION2017 ~ Present
・
Within one month
Full-time / Interested in working remotely
6-10 years
Southern Taiwan University of Science and Technology
・
department of mechanical engineering
機構課長 @大日科技股份有限公司2023 ~ Present
・
機械工程師、振動工程師、裝機工程師、設備工程師
Within one month
學, 碩士學位, 機械與精密工程研究所與博士班, 2005年 ~ 2010年 博班二年級休學,申請研發替代役。 協助指導教授壓電材料實驗與ANSYS分析 ( IEEE Journal,中工會論文集,。 圓盤形壓電變壓器之研究 ( 碩士論文,。 證照 工程相關 丙級室內配線與鉗工技術士。 單一級固定式
Employed
Taiwan
Full-time / Interested in working remotely
10-15 years
Newtype International Language School
・
英文
PhD Candidate @國立清華大學 National Tsing Hua University2021 ~ Present
・
Senior Engineer, Research and Development Engineer, Advanced Packaging Engineer
Within one month
@gmail.comHsinchu, Hsinchu City, Taiwan Skills Research Expertise Linear and Nonlinear Photonics Plasmonics Optical Spintronics Silicon Photonics Confocal Microscopy and Interferometry Mathematical and Numerical Modeling F inite D ifference T ime D omain Method F inite D ifference E lement Method C oupled M ode T heory Softwares ANSYS FDTD ANSYS FDE/MODE ANSYS INTERCONNECT Klayout COMSOL Multiphysics Luceda Qutip Programming MATLAB Python Mathematica Soft Skills Problem-Solving Resilience Adaptability Leadership Scientific Research Paper writing Communication Public Speaking Languages English (native) Hindi (native) Mandarin (beginner) Kannada (native) Work Experience PhD Candidate National Tsing Hua University • FebruaryPresent Embarked
Studying
Taiwan
Intern / Not interested in working remotely
4-6 years
國立清華大學 National Tsing Hua University
・
Photonics, Physics, Optics
Offline
Offline
Principal Engineer @TSMC2021 ~ Present
・
Within one month
design methodology in advanced nodes (7/6/5/4/3nm) Design implementation from netlist to tape-out and PPA assessment in 7/6/5/4/3nm technologies Proven knowledge of Cadence Innovus and Synopsys ICC2/FusionCompiler backend design flow Familiar with Ansys Redhawk/Redhawk-CPA EM/IR methodology CUSTOMER ENGAGEMENT, SUPPORT, and EDUCATION Coordinate technical support to customers in the above areas of profession Proactive and close collaboration with EDA vendors Conduct technological training courses and technical application notes for partners/customers Education NATIONAL CHIAO TUNG UNIVERSITY,M
Employed
・
Not open to opportunities
Taiwan
Full-time / Interested in working remotely
6-10 years
National Chiao Tung University
・
Electronics Engineering
Deputy R&D Manager @Cyntec (Delta Electronics Group)2023 ~ Present
・
PM/產品經理/專案管理
Within one month
schedule. Senior Engineer • Cyntec (Delta Electronics Group) 五月十二月 2020 [FAE / Product development] ．Increased over $100M of revenue by cooperating with customers to design the novel power inductor / choke for smartphone PMIC, SiP in smartwatches and ultra-thin size request in TWS. ．Combined Ansys software like Maxwell and Workbench to simulate material and structure of the wireless charging coil. ．Operated experiments and developed a new process platform for power inductor / choke. 學歷National Tsing Hua University Materials Sciences and EngineeringNational Tsing Hua University Materials Sciences and Engineering 技能
Employed
Taiwan
Full-time / Interested in working remotely
6-10 years
National Tsing Hua University
・
Materials Sciences and EngineeringThe Most Lightweight and Effective Recruiting Plan
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Professional Background
Current status
Employed
Job Search Progress
Not open to opportunities
Professions
Other
Fields of Employment
Semiconductor
Work experience
6-10 years
Management
None
Skills
Languages
Chinese
・
Native or Bilingual
English
・
Fluent
Job search preferences
Positions
Job types
Full-time
Locations
Taiwan, 台灣
Remote
Interested in working remotely
Freelance
No
Educations
School
National Chiao Tung University
Major
Electronics Engineering
Kuan-Ting Chen
Physical design engineer with 10 years of experience working in the semiconductors industry. Skilled in cell-based ASIC/SoC implementation and power integrity (EM/IR) analysis methodology, especially for advanced nodes (7/6/5/4/3nm). Familiar with Tcl/Perl scripting and design automation. Coordinate technical support and customer engagement with close collaboration with EDA vendors. Organize technological education to partners/customers. Fluent in Mandarin and English (TOEFL: 105/120).[email protected]
+886-921672917
Hsinchu, Taiwan
Engineering Skills
PHYSICAL DESIGN
- Establish and deploy physical design methodology in advanced nodes (7/6/5/4/3nm)
- Design implementation from netlist to tape-out and PPA assessment in 7/6/5/4/3nm technologies
- Proven knowledge of Cadence Innovus and Synopsys ICC2/FusionCompiler backend design flow
- Familiar with Ansys Redhawk/Redhawk-CPA EM/IR methodology
- Coordinate technical support to customers in the above areas of profession
- Proactive and close collaboration with EDA vendors
- Conduct technological training courses and technical application notes for partners/customers
Education
NATIONAL CHIAO TUNG UNIVERSITY, 2011 - 2013
M. Sc. of Electronics Engineering
NATIONAL CHIAO TUNG UNIVERSITY, 2007 - 2011
B.S. of Electronics Engineering
Professional Experience
INTEL CORPORATION, 2022 - Present
Physical Design Engineer, Design Service Engineering
- 3DIC testchip execution
- Heterogeneous integration flow enablement
TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD., 2019 - 2022
Principal Engineer, Design Technology Platform
- 6nm HPC segment customer engagement, flow pipeclean, and project on-site field support
- 5/4/3nm HPC segment customer engagement, PPA assessment, and technical support
- 5/4/3nm node EDA enablement and certification program
- 20+ physical implementation flow trainings to customers in 7/6/5/3 nm technologies
GLOBAL UNICHIP CORPORATION, 2013 - 2019
Deputy Technical Manager, Design Service
- 7nm HPC peripheral block implementation (2M inst.; P&R, timing closure, DRC/LVS)
- 7nm GPU block implementation (1M inst.; P&R, path-finding, customer field support)
- 7nm physical design flow and DDR IP hardening (P&R, timing closure, DRC/LVS, field support)
- 5+ power integrity analysis projects in 28/16nm technology
- 20+ APR and/or power integrity project support experience in sub-28nm nodes
Kuan-Ting Chen
Physical design engineer with 10 years of experience working in the semiconductors industry. Skilled in cell-based ASIC/SoC implementation and power integrity (EM/IR) analysis methodology, especially for advanced nodes (7/6/5/4/3nm). Familiar with Tcl/Perl scripting and design automation. Coordinate technical support and customer engagement with close collaboration with EDA vendors. Organize technological education to partners/customers. Fluent in Mandarin and English (TOEFL: 105/120).[email protected]
+886-921672917
Hsinchu, Taiwan
Engineering Skills
PHYSICAL DESIGN
- Establish and deploy physical design methodology in advanced nodes (7/6/5/4/3nm)
- Design implementation from netlist to tape-out and PPA assessment in 7/6/5/4/3nm technologies
- Proven knowledge of Cadence Innovus and Synopsys ICC2/FusionCompiler backend design flow
- Familiar with Ansys Redhawk/Redhawk-CPA EM/IR methodology
- Coordinate technical support to customers in the above areas of profession
- Proactive and close collaboration with EDA vendors
- Conduct technological training courses and technical application notes for partners/customers
Education
NATIONAL CHIAO TUNG UNIVERSITY, 2011 - 2013
M. Sc. of Electronics Engineering
NATIONAL CHIAO TUNG UNIVERSITY, 2007 - 2011
B.S. of Electronics Engineering
Professional Experience
INTEL CORPORATION, 2022 - Present
Physical Design Engineer, Design Service Engineering
- 3DIC testchip execution
- Heterogeneous integration flow enablement
TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD., 2019 - 2022
Principal Engineer, Design Technology Platform
- 6nm HPC segment customer engagement, flow pipeclean, and project on-site field support
- 5/4/3nm HPC segment customer engagement, PPA assessment, and technical support
- 5/4/3nm node EDA enablement and certification program
- 20+ physical implementation flow trainings to customers in 7/6/5/3 nm technologies
GLOBAL UNICHIP CORPORATION, 2013 - 2019
Deputy Technical Manager, Design Service
- 7nm HPC peripheral block implementation (2M inst.; P&R, timing closure, DRC/LVS)
- 7nm GPU block implementation (1M inst.; P&R, path-finding, customer field support)
- 7nm physical design flow and DDR IP hardening (P&R, timing closure, DRC/LVS, field support)
- 5+ power integrity analysis projects in 28/16nm technology
- 20+ APR and/or power integrity project support experience in sub-28nm nodes